// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//
// IP LIB INDEX : 
// IP Name      : 
//                
// File name    :	 schedule_top
// Module name  :  schedule_top
// Full name    :  schedule_top
//
// Author       :  Hbing 
// Email        :  2629029232@qq.com
// Data         :  2020/8/24
// Version      :  V 1.0 
// 
//Abstract      :
// Called by    :  Father Module
// 
// Modification history
// ------------------------------------------------------------------------------------------------------
// 	v1.1 zhangjianyuan 4.19
//	
//  
// *********************************************************************
 `include "top_define.v"
// *******************
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 

// *******************
// DESCRIPTION
// *******************
// 
// 
//*******************
//DEFINE(s)
//*******************
//`define UDLY 1    //Unit delay, for non-blocking assignments in sequential logic

//*******************
//DEFINE MODULE PORT
module schedule_top(
	//sysrem input/output
	input  wire 		clk  ,
	input  wire 		rst_n,
    input  wire  [9:0]  ram_2p_cfg_register,
	//queue_schedule init_done
	output wire 		init_done,
	//cpu interface 
`ifndef NO_CPU_MODE
	output reg 	[31:0] 	np_data_out,
	input  wire [31:0] 	np_data_in ,
	input  wire [16:0] 	np_addr_in ,
	input  wire [ 1:0]  np_addr_ctrl,	

	output wire sch_rd_vld,
	//\u65b0\u589eCPU\u914d\u7f6eDWRR\u6743\u91cd\u4ee5\u53ca\u5f00\u542f\u4f7f\u80fd
`else
    input  wire         DWRR_en,
    input  wire [ 15:0] WEIGHT7,
    input  wire [ 15:0] WEIGHT6,
    input  wire [ 15:0] WEIGHT5,
    input  wire [ 15:0] WEIGHT4,
    input  wire [ 15:0] WEIGHT3,
    input  wire [ 15:0] WEIGHT2,
    input  wire [ 15:0] WEIGHT1,
    input  wire [ 15:0] WEIGHT0,
	// CPU config threshold
		//	enqueue
	output wire [  2:0] query_CPU_node_minmax_threshold,  //\u8282\u70b9\u6700\u5c0f\u6700\u5927\u95e8\u9650
	input  wire [ 31:0] CPU_node_minmax_threshold_data ,
	output wire [  5:0] query_CPU_queue_max_threshold  ,  //\u961f\u5217\u6700\u5927\u95e8\u9650
	input  wire [ 31:0] CPU_queue_max_threshold_data   ,
	input  wire [ 31:0] CPU_BD_public_length           ,  //BD\u5171\u4eab\u533a\u5927\u5c0f
	//	//	dequeue
	output wire [ 2:0]  query_CPU_node_min_threshold,
	input  wire [31:0]  CPU_node_min_threshold_data ,

	// cpu_register
	output wire [31:0]  ro_reg_np_freeblocknumber_register	,
	output wire [31:0]  ro_reg_np_mac_enqueue_cnt 			,	   
	output wire [31:0]  ro_reg_np_mac_enqueue_fail_cnt 		, 
	output wire [31:0]  ro_reg_np_enqueue_num 				,
	output wire [31:0]  ro_reg_np_dequeue_num 				,		
	output wire [31:0]  ro_reg_np_max_rx_length 			,
	output wire [31:0]  ro_reg_np_max_tx_length   			,
    output wire [31:0]  rx_frame_cnt_node_0                 ,
    output wire [31:0]  rx_frame_cnt_node_1                 ,
    output wire [31:0]  rx_frame_cnt_node_2                 ,
    output wire [31:0]  rx_frame_cnt_node_3                 ,
    output wire [31:0]  rx_frame_cnt_node_4                 ,
    output wire [31:0]  tx_frame_cnt_node_0                 ,
    output wire [31:0]  tx_frame_cnt_node_1                 ,
    output wire [31:0]  tx_frame_cnt_node_2                 ,
    output wire [31:0]  tx_frame_cnt_node_3                 ,
    output wire [31:0]  tx_frame_cnt_node_4                 ,    
`endif
	//with receive_schedule
	(*mark_debug = "true"*)input  wire [ 31:0] rx_fifo_wdata,
	(*mark_debug = "true"*)input  wire 		rx_fifo_wren ,
	(*mark_debug = "true"*)output wire 		rx_fifo_full ,
	//with frame_process
	input  wire         trans_ready   	,
	output wire         trans_start   	,
	output wire 	    discard_start 	,
	input  wire 		frame_rd_end    ,
	input  wire [255:0] bus_data_i    ,
	input  wire         bus_data_val_i,
	//input  wire         bus_data_end_i,
	//input  wire [ 10:0] frame_len_bus ,
	//with crossbar_ctrl_top
	(*mark_debug = "true"*)input  wire 		uni_tx_rdy0,
	(*mark_debug = "true"*)input  wire 		uni_tx_rdy1,
	(*mark_debug = "true"*)input  wire 		uni_tx_rdy2,
	(*mark_debug = "true"*)input  wire 		uni_tx_rdy3,
	(*mark_debug = "true"*)input  wire 		mul_tx_rdy0,
	(*mark_debug = "true"*)input  wire 		mul_tx_rdy1,
	(*mark_debug = "true"*)input  wire 		mul_tx_rdy2,
	(*mark_debug = "true"*)input  wire 		mul_tx_rdy3,
	output wire [255:0] emac_data_in    ,
	(*mark_debug = "true"*)output wire         emac_data_wren  ,
	(*mark_debug = "true"*)output wire [  5:0] rx_address_dpram,
	(*mark_debug = "true"*)output wire [  3:0] mac_dest_port_in,
	(*mark_debug = "true"*)output wire         mul_indicate    
	);

//*******************
//DEFINE PARAMETER
//*******************
//Parameter(s) 

//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS

//WIRES
wire 		 rst 	;
//weight
`ifndef NO_CPU_MODE
wire [ 16:0] DWRR_en;
wire [ 15:0] WEIGHT7;
wire [ 15:0] WEIGHT6;
wire [ 15:0] WEIGHT5;
wire [ 15:0] WEIGHT4;
wire [ 15:0] WEIGHT3;
wire [ 15:0] WEIGHT2;
wire [ 15:0] WEIGHT1;
wire [ 15:0] WEIGHT0;

// CPU config threshold
	//	enqueue
wire [  2:0] query_CPU_node_minmax_threshold;  //\u8282\u70b9\u6700\u5c0f\u6700\u5927\u95e8\u9650
wire [ 31:0] CPU_node_minmax_threshold_data ;
wire [  5:0] query_CPU_queue_max_threshold  ;  //\u961f\u5217\u6700\u5927\u95e8\u9650
wire [ 31:0] CPU_queue_max_threshold_data   ;
wire [ 31:0] CPU_BD_public_length           ;  //BD\u5171\u4eab\u533a\u5927\u5c0f
//	//	dequeue
wire [ 2:0]  query_CPU_node_min_threshold;
wire [31:0]  CPU_node_min_threshold_data ;

// cpu_register
wire [31:0]  ro_reg_np_freeblocknumber_register	;
wire [31:0]  ro_reg_np_mac_enqueue_cnt 			;	   
wire [31:0]  ro_reg_np_mac_enqueue_fail_cnt 	; 
wire [31:0]  ro_reg_np_enqueue_num 				;
wire [31:0]  ro_reg_np_dequeue_num 				;		
wire [31:0]  ro_reg_np_max_rx_length 			;
wire [31:0]  ro_reg_np_max_tx_length   			;
wire [31:0]  rx_frame_cnt_node_0                 ;
wire [31:0]  rx_frame_cnt_node_1                 ;
wire [31:0]  rx_frame_cnt_node_2                 ;
wire [31:0]  rx_frame_cnt_node_3                 ;
wire [31:0]  rx_frame_cnt_node_4                 ;
wire [31:0]  tx_frame_cnt_node_0                 ;
wire [31:0]  tx_frame_cnt_node_1                 ;
wire [31:0]  tx_frame_cnt_node_2                 ;
wire [31:0]  tx_frame_cnt_node_3                 ;
wire [31:0]  tx_frame_cnt_node_4                 ; 
`endif
//FIFO
//\u63a5\u6536\u8c03\u5ea6--rx_fifo--\u5165\u961f\u603b\u8c03\u5ea6
// wire [31:0] rx_fifo_wdata;
// wire 		rx_fifo_wren;
(*mark_debug = "true"*)wire 		rx_fifo_rden;
(*mark_debug = "true"*)wire [31:0] rx_fifo_rdata;
// wire 		rx_fifo_full;
(*mark_debug = "true"*)wire 		rx_fifo_empty;
//\u5165\u961f\u603b\u8c03\u5ea6--enqueue_result_fifo--\u63a5\u6536\u603b\u7ebf
(*mark_debug = "true"*)wire 		enqueue_result_fifo_wdata;
(*mark_debug = "true"*)wire 		enqueue_result_fifo_wren;
(*mark_debug = "true"*)wire 		enqueue_result_fifo_rden;
(*mark_debug = "true"*)wire 		enqueue_result_fifo_rdata;
(*mark_debug = "true"*)wire 		enqueue_result_fifo_full;
(*mark_debug = "true"*)wire 		enqueue_result_fifo_empty;
//\u5165\u961f\u603b\u8c03\u5ea6--sr_rx_fifo--\u63a5\u6536\u603b\u7ebf
(*mark_debug = "true"*)wire [39:0] sr_rx_fifo_wdata;
(*mark_debug = "true"*)wire 		sr_rx_fifo_wren;
(*mark_debug = "true"*)wire 		sr_rx_fifo_rden;
(*mark_debug = "true"*)wire [39:0] sr_rx_fifo_rdata;
(*mark_debug = "true"*)wire 		sr_rx_fifo_full;
(*mark_debug = "true"*)wire 		sr_rx_fifo_empty;
// wire [ 6:0] sr_rx_fifo_cnt;
//\u51fa\u961f\u603b\u8c03\u5ea6--sr_rx_mul_fifo--tx_fifo\u53d1\u9001\u8bf7\u6c42
(*mark_debug = "true"*)wire [ 3:0] sr_rx_mul_fifo_wdata;
(*mark_debug = "true"*)wire 		sr_rx_mul_fifo_wren;
(*mark_debug = "true"*)wire 		sr_rx_mul_fifo_rden;
(*mark_debug = "true"*)wire [ 3:0] sr_rx_mul_fifo_rdata;
(*mark_debug = "true"*)wire 		sr_rx_mul_fifo_full;
(*mark_debug = "true"*)wire 		sr_rx_mul_fifo_empty;
//\u53d1\u9001\u8bf7\u6c42--tx_fifo--\u51fa\u961f\u603b\u8c03\u5ea6
(*mark_debug = "true"*)wire [ 9:0] tx_fifo_wdata_mul;
(*mark_debug = "true"*)wire 		tx_fifo_wren_mul;
(*mark_debug = "true"*)wire 		tx_fifo_rden_mul;
(*mark_debug = "true"*)wire [ 9:0] tx_fifo_rdata_mul;
(*mark_debug = "true"*)wire 		tx_fifo_full_mul;
(*mark_debug = "true"*)wire 		tx_fifo_empty_mul;

(*mark_debug = "true"*)wire [ 5:0] tx_fifo_wdata_7;
(*mark_debug = "true"*)wire 		tx_fifo_wren_7;
(*mark_debug = "true"*)wire 		tx_fifo_rden_7;
(*mark_debug = "true"*)wire [ 5:0] tx_fifo_rdata_7;
(*mark_debug = "true"*)wire 		tx_fifo_full_7;
(*mark_debug = "true"*)wire 		tx_fifo_empty_7;

wire [ 5:0] tx_fifo_wdata_6;
wire 		tx_fifo_wren_6;
wire 		tx_fifo_rden_6;
wire [ 5:0] tx_fifo_rdata_6;
wire 		tx_fifo_full_6;
wire 		tx_fifo_empty_6;

wire [ 5:0] tx_fifo_wdata_5;
wire 		tx_fifo_wren_5;
wire 		tx_fifo_rden_5;
wire [ 5:0] tx_fifo_rdata_5;
wire 		tx_fifo_full_5;
wire 		tx_fifo_empty_5;

wire [ 5:0] tx_fifo_wdata_4;
wire 		tx_fifo_wren_4;
wire 		tx_fifo_rden_4;
wire [ 5:0] tx_fifo_rdata_4;
wire 		tx_fifo_full_4;
wire 		tx_fifo_empty_4;

wire [ 5:0] tx_fifo_wdata_3;
wire 		tx_fifo_wren_3;
wire 		tx_fifo_rden_3;
wire [ 5:0] tx_fifo_rdata_3;
wire 		tx_fifo_full_3;
wire 		tx_fifo_empty_3;

wire [ 5:0] tx_fifo_wdata_2;
wire 		tx_fifo_wren_2;
wire 		tx_fifo_rden_2;
wire [ 5:0] tx_fifo_rdata_2;
wire 		tx_fifo_full_2;
wire 		tx_fifo_empty_2;

wire [ 5:0] tx_fifo_wdata_1;
wire 		tx_fifo_wren_1;
wire 		tx_fifo_rden_1;
wire [ 5:0] tx_fifo_rdata_1;
wire 		tx_fifo_full_1;
wire 		tx_fifo_empty_1;

(*mark_debug = "true"*)wire [ 5:0] tx_fifo_wdata_0;
(*mark_debug = "true"*)wire 		tx_fifo_wren_0;
(*mark_debug = "true"*)wire 		tx_fifo_rden_0;
(*mark_debug = "true"*)wire [ 5:0] tx_fifo_rdata_0;
(*mark_debug = "true"*)wire 		tx_fifo_full_0;
(*mark_debug = "true"*)wire 		tx_fifo_empty_0;

//\u51fa\u961f\u603b\u8c03\u5ea6--sr_tx_fifo--\u53d1\u9001\u603b\u7ebf
(*mark_debug = "true"*)wire [47:0] sr_tx_fifo_wdata_mul;
(*mark_debug = "true"*)wire 		sr_tx_fifo_wren_mul;
(*mark_debug = "true"*)wire 		sr_tx_fifo_rden_mul;
(*mark_debug = "true"*)wire [47:0] sr_tx_fifo_rdata_mul;
(*mark_debug = "true"*)wire 		sr_tx_fifo_full_mul;
(*mark_debug = "true"*)wire 		sr_tx_fifo_empty_mul;
// wire [ 7:0] sr_tx_fifo_cnt_mul;

(*mark_debug = "true"*)wire [47:0] sr_tx_fifo_wdata_7;
(*mark_debug = "true"*)wire 		sr_tx_fifo_wren_7;
(*mark_debug = "true"*)wire 		sr_tx_fifo_rden_7;
(*mark_debug = "true"*)wire [47:0] sr_tx_fifo_rdata_7;
(*mark_debug = "true"*)wire 		sr_tx_fifo_full_7;
(*mark_debug = "true"*)wire 		sr_tx_fifo_empty_7;
// wire [ 7:0] sr_tx_fifo_cnt_7;

wire [47:0] sr_tx_fifo_wdata_6;
wire 		sr_tx_fifo_wren_6;
wire 		sr_tx_fifo_rden_6;
wire [47:0] sr_tx_fifo_rdata_6;
wire 		sr_tx_fifo_full_6;
wire 		sr_tx_fifo_empty_6;
// wire [ 7:0] sr_tx_fifo_cnt_6;

wire [47:0] sr_tx_fifo_wdata_5;
wire 		sr_tx_fifo_wren_5;
wire 		sr_tx_fifo_rden_5;
wire [47:0] sr_tx_fifo_rdata_5;
wire 		sr_tx_fifo_full_5;
wire 		sr_tx_fifo_empty_5;
// wire [ 7:0] sr_tx_fifo_cnt_5;

wire [47:0] sr_tx_fifo_wdata_4;
wire 		sr_tx_fifo_wren_4;
wire 		sr_tx_fifo_rden_4;
wire [47:0] sr_tx_fifo_rdata_4;
wire 		sr_tx_fifo_full_4;
wire 		sr_tx_fifo_empty_4;
// wire [ 7:0] sr_tx_fifo_cnt_4;

wire [47:0] sr_tx_fifo_wdata_3;
wire 		sr_tx_fifo_wren_3;
wire 		sr_tx_fifo_rden_3;
wire [47:0] sr_tx_fifo_rdata_3;
wire 		sr_tx_fifo_full_3;
wire 		sr_tx_fifo_empty_3;
// wire [ 7:0] sr_tx_fifo_cnt_3;

wire [47:0] sr_tx_fifo_wdata_2;
wire 		sr_tx_fifo_wren_2;
wire 		sr_tx_fifo_rden_2;
wire [47:0] sr_tx_fifo_rdata_2;
wire 		sr_tx_fifo_full_2;
wire 		sr_tx_fifo_empty_2;
// wire [ 7:0] sr_tx_fifo_cnt_2;

wire [47:0] sr_tx_fifo_wdata_1;
wire 		sr_tx_fifo_wren_1;
wire 		sr_tx_fifo_rden_1;
wire [47:0] sr_tx_fifo_rdata_1;
wire 		sr_tx_fifo_full_1;
wire 		sr_tx_fifo_empty_1;
// wire [ 7:0] sr_tx_fifo_cnt_1;

(*mark_debug = "true"*)wire [47:0] sr_tx_fifo_wdata_0;
(*mark_debug = "true"*)wire 		sr_tx_fifo_wren_0;
(*mark_debug = "true"*)wire 		sr_tx_fifo_rden_0;
(*mark_debug = "true"*)wire [47:0] sr_tx_fifo_rdata_0;
(*mark_debug = "true"*)wire 		sr_tx_fifo_full_0;
(*mark_debug = "true"*)wire 		sr_tx_fifo_empty_0;
// wire [ 7:0] sr_tx_fifo_cnt_0;
//\u53d1\u9001\u603b\u7ebf--release_addr_fifo--\u7f13\u5b58\u7ba1\u7406
wire [17:0] release_addr_fifo_wdata;
wire 		release_addr_fifo_wren;
wire 		release_addr_fifo_rden;
wire [17:0] release_addr_fifo_rdata;
wire 		release_addr_fifo_full;
wire 		release_addr_fifo_empty;
// wire [ 6:0] release_addr_fifo_cnt;

//LINK
//\u5165\u961f\u603b\u8c03\u5ea6-\u961f\u5217\u4fe1\u606f\u7ba1\u7406
wire 		enqueue_head_infor_wr_en    ;
wire [ 5:0] enqueue_head_infor_wr_addr  ;
wire [31:0] enqueue_head_infor_wr_data  ;
wire [31:0] enqueue_head_infor_rd_data  ;
wire 	 	enqueue_tail_infor_wr_en    ;
wire [ 5:0] enqueue_tail_infor_wr_addr  ;
wire [15:0] enqueue_tail_infor_wr_data  ;
wire [15:0] enqueue_tail_infor_rd_data  ;
wire 	 	enqueue_length_infor_wr_en  ;
wire [ 5:0] enqueue_length_infor_wr_addr;
wire [15:0] enqueue_length_infor_wr_data;
wire [15:0] enqueue_length_infor_rd_data;
// wire 	 	queue_length_wren_b         ;
// wire [ 5:0] queue_length_addr_b         ;
// wire [15:0] queue_length_din_b          ;
wire 	 	enqueue_node_length_wr_en   ;
wire [ 2:0] enqueue_node_length_wr_addr ;
wire [15:0] enqueue_node_length_wr_data ;
wire [15:0] enqueue_node_length_rd_data ;
// wire  		node_length_wren_b          ;
// wire [ 2:0] node_length_addr_b          ;
// wire [15:0] node_length_din_b           ;
//\u5165\u961f\u603b\u8c03\u5ea6--\u7f13\u5b58\u7ba1\u7406
wire [31:0] BD_public_used               ;
wire 		mem_management_init_done     ;
wire 		mem_allocate_request         ; 
wire [15:0] mem_allocate_address         ;
wire 		mem_free_BD_fifo_empty       ;
wire [ 5:0]	enqueue_Linked_list_ram_wren ; 
wire [11:0] enqueue_Linked_list_ram_waddr;
wire [47:0] enqueue_Linked_list_ram_wdata;
wire 		enqueue_BD_public_used_update_en ;
wire [31:0] enqueue_BD_public_used_update_num;
//\u5165\u961f\u603b\u8c03\u5ea6--\u51fa\u961f\u603b\u8c03\u5ea6
wire 		queue_mem_init_done   ;
wire 		enqueue_executing_flag;
wire [ 5:0] enqueue_number        ;
wire 		queue_head_update_done;
wire 		dequeue_executing_flag;
wire [ 5:0] dequeue_number        ;
//\u961f\u5217\u4fe1\u606f\u7ba1\u7406--\u51fa\u961f\u603b\u8c03\u5ea6
wire 		dequeue_head_infor_wr_en  ;
wire [ 5:0] dequeue_head_infor_wr_addr;
wire [31:0] dequeue_head_infor_wr_data;
wire [31:0] dequeue_head_infor_rd_data;
wire 		dequeue_tail_infor_wr_en  ;
wire [ 5:0] dequeue_tail_infor_wr_addr;
wire [15:0] dequeue_tail_infor_wr_data;
// wire [15:0] dequeue_tail_infor_rd_data;
wire 		dequeue_length_infor_wr_en  ;
wire [ 5:0] dequeue_length_infor_wr_addr;
wire [15:0] dequeue_length_infor_wr_data;
wire [15:0] dequeue_length_infor_rd_data;
// wire 		queue_length_wren_a;
// wire [ 5:0] queue_length_addr_a;
// wire [15:0] queue_length_din_a ;
wire 		dequeue_node_length_wr_en  ;
wire [ 2:0] dequeue_node_length_wr_addr;
wire [15:0] dequeue_node_length_wr_data;
wire [15:0] dequeue_node_length_rd_data;
// wire 		node_length_wren_a;
// wire [ 2:0] node_length_addr_a;
// wire [15:0] node_length_din_a ;
//\u961f\u5217\u4fe1\u606f\u7ba1\u7406--\u63a5\u6536\u603b\u7ebf
wire        enqueue_indicate_length_wr_en  ;
wire [ 2:0] enqueue_indicate_length_wr_addr;
wire [63:0] enqueue_indicate_length_wr_data;
wire [63:0] enqueue_indicate_length_rd_data;
//\u961f\u5217\u4fe1\u606f\u7ba1\u7406--\u53d1\u9001\u8bf7\u6c42
wire        dequeue_indicate_length_wr_en  ;
wire [ 2:0] dequeue_indicate_length_wr_addr;
wire [63:0] dequeue_indicate_length_wr_data;
//\u7f13\u5b58\u7ba1\u7406--\u51fa\u961f\u603b\u8c03\u5ea6
wire 		dequeue_BD_public_used_update_en ;
wire [31:0] dequeue_BD_public_used_update_num;
wire [11:0] dequeue_Linked_list_ram_raddr;
wire [47:0] dequeue_Linked_list_ram_rdata;
//\u63a5\u6536\u603b\u7ebf--\u5206\u7ec4\u5904\u7406
// wire         trans_ready   ;
// wire         trans_start   ;
// wire [255:0] bus_data_i    ;
// wire         bus_data_val_i;
// wire         bus_data_end_i;
// wire [ 10:0] frame_len_bus ;
wire 		queue_indicate_ram_init_done;
//\u63a5\u6536\u603b\u7ebf--\u7247\u5185\u7f13\u5b58
(*mark_debug = "true"*)wire [ 13:0] memory_waddr;
(*mark_debug = "true"*)wire         memory_wren ;
wire [255:0] memory_wdata;
//\u63a5\u6536\u603b\u7ebf--bit\u63a9\u7801\u8868
wire [ 2:0] port_state_bit_set;
wire  		port_state_bit_val;
//bit\u63a9\u7801\u8868--\u53d1\u9001\u8bf7\u6c42
// wire [ 2:0] port_state_bit_clear;
// wire [ 4:0] port_state_bit      ;
//\u53d1\u9001\u8bf7\u6c42--\u4ea4\u53c9\u8282\u70b9
// wire 		uni_tx_rdy0;
// wire 		uni_tx_rdy1;
// wire 		uni_tx_rdy2;
// wire 		uni_tx_rdy3;
// wire 		mul_tx_rdy0;
// wire 		mul_tx_rdy1;
// wire 		mul_tx_rdy2;
// wire 		mul_tx_rdy3;
//\u53d1\u9001\u603b\u7ebf--\u7247\u5185\u7f13\u5b58\u533a
(*mark_debug = "true"*)wire [ 13:0] memory_raddr;
(*mark_debug = "true"*)wire         memory_rden ;
wire [255:0] memory_rdata;
//\u7aef\u53e3\u6709\u6548\uff0c\u8ba4\u4e3a\u53ef\u4ee5\u53d1\u9001\u548c\u6b63\u5728\u53d1\u9001\u65f6\u5747\u7aef\u53e3\u6709\u6548
(*mark_debug = "true"*)wire 		uni_port_val0;
(*mark_debug = "true"*)wire 		uni_port_val1;
(*mark_debug = "true"*)wire 		uni_port_val2;
(*mark_debug = "true"*)wire 		uni_port_val3;
(*mark_debug = "true"*)wire 		mul_port_val0;
(*mark_debug = "true"*)wire 		mul_port_val1;
(*mark_debug = "true"*)wire 		mul_port_val2;
(*mark_debug = "true"*)wire 		mul_port_val3;

// wire [255:0] emac_data_in    ;
// wire         emac_data_wren  ;
// wire [  5:0] rx_address_dpram;
// wire [  3:0] mac_dest_port_in;
// wire         mul_indicate    ;
//*********************
//INSTANTCE MODULE
//*********************
//\u63a5\u6536\u4fe1\u606fFIFO
`ifdef ASIC
rx_fifo_fwft inst_rx_fifo_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(rx_fifo_wdata),
	.w_we(rx_fifo_wren),
	.w_full(rx_fifo_full),
	.w_afull(),
	
	.r_data(rx_fifo_rdata),
	.r_re(rx_fifo_rden),
	.r_empty(rx_fifo_empty),
	.r_aempty()	
);
`else
rx_fifo inst_rx_fifo (
  .clk  (clk           ),  // input wire clk
  .rst  (rst        ),  // input wire rst
  .din  (rx_fifo_wdata ),  // input wire [31 : 0] din
  .wr_en(rx_fifo_wren  ),  // input wire wr_en
  .rd_en(rx_fifo_rden  ),  // input wire rd_en
  .dout (rx_fifo_rdata ),  // output wire [31 : 0] dout
  .full (rx_fifo_full  ),  // output wire full
  .empty(rx_fifo_empty )   // output wire empty
);
`endif
	schedule_enqueue inst_schedule_enqueue(
			.clk                               (clk),
			.rst_n                             (rst_n),
			.init_done                         (queue_mem_init_done),
			.rx_fifo_empty                     (rx_fifo_empty),
			.rx_fifo_rden                      (rx_fifo_rden),
			.rx_fifo_rdata                     (rx_fifo_rdata),
			.sr_rx_fifo_full                   (sr_rx_fifo_full),
			.sr_rx_fifo_wren                   (sr_rx_fifo_wren),
			.sr_rx_fifo_wdata                  (sr_rx_fifo_wdata),
			// .sr_rx_fifo_cnt                    (sr_rx_fifo_cnt),
			.query_CPU_node_minmax_threshold   (query_CPU_node_minmax_threshold),
			.CPU_node_minmax_threshold_data    (CPU_node_minmax_threshold_data),
			.query_CPU_queue_max_threshold     (query_CPU_queue_max_threshold),
			.CPU_queue_max_threshold_data      (CPU_queue_max_threshold_data),
			.CPU_BD_public_length              (CPU_BD_public_length),
			.ro_reg_np_mac_enqueue_cnt	       (ro_reg_np_mac_enqueue_cnt	  ),
			.ro_reg_np_mac_enqueue_fail_cnt    (ro_reg_np_mac_enqueue_fail_cnt), 
			.ro_reg_np_enqueue_num		       (ro_reg_np_enqueue_num		  ),
			.ro_reg_np_max_rx_length 		   (ro_reg_np_max_rx_length       ),
            .rx_frame_cnt_node_0               (rx_frame_cnt_node_0           ) ,
            .rx_frame_cnt_node_1               (rx_frame_cnt_node_1           ) ,
            .rx_frame_cnt_node_2               (rx_frame_cnt_node_2           ) ,
            .rx_frame_cnt_node_3               (rx_frame_cnt_node_3           ) ,
            .rx_frame_cnt_node_4               (rx_frame_cnt_node_4           ) ,
			.enqueue_head_infor_wr_en          (enqueue_head_infor_wr_en),
			.enqueue_head_infor_wr_addr        (enqueue_head_infor_wr_addr),
			.enqueue_head_infor_wr_data        (enqueue_head_infor_wr_data),
			//.enqueue_head_infor_rd_data        (enqueue_head_infor_rd_data),
			.enqueue_tail_infor_wr_en          (enqueue_tail_infor_wr_en),
			.enqueue_tail_infor_wr_addr        (enqueue_tail_infor_wr_addr),
			.enqueue_tail_infor_wr_data        (enqueue_tail_infor_wr_data),
			.enqueue_tail_infor_rd_data        (enqueue_tail_infor_rd_data),
			.dequeue_tail_infor_wr_en  		   (dequeue_tail_infor_wr_en  ),
			.dequeue_tail_infor_wr_addr		   (dequeue_tail_infor_wr_addr),
			.dequeue_tail_infor_wr_data		   (dequeue_tail_infor_wr_data),
			.enqueue_length_infor_wr_en        (enqueue_length_infor_wr_en),
			.enqueue_length_infor_wr_addr      (enqueue_length_infor_wr_addr),
			.enqueue_length_infor_wr_data      (enqueue_length_infor_wr_data),
			.enqueue_length_infor_rd_data      (enqueue_length_infor_rd_data),

			.dequeue_length_infor_wr_en        (dequeue_length_infor_wr_en  ),
			.dequeue_length_infor_wr_addr      (dequeue_length_infor_wr_addr),
			.dequeue_length_infor_wr_data      (dequeue_length_infor_wr_data),
			// .queue_length_wren_b               (queue_length_wren_b),
			// .queue_length_addr_b               (queue_length_addr_b),
			// .queue_length_din_b                (queue_length_din_b),
			.enqueue_node_length_wr_en         (enqueue_node_length_wr_en),
			.enqueue_node_length_wr_addr       (enqueue_node_length_wr_addr),
			.enqueue_node_length_wr_data       (enqueue_node_length_wr_data),
			.enqueue_node_length_rd_data       (enqueue_node_length_rd_data),

			.dequeue_node_length_wr_en         (dequeue_node_length_wr_en   ),
			.dequeue_node_length_wr_addr       (dequeue_node_length_wr_addr ),
			.dequeue_node_length_wr_data       (dequeue_node_length_wr_data ),			
			// .node_length_wren_b                (node_length_wren_b),
			// .node_length_addr_b                (node_length_addr_b),
			// .node_length_din_b                 (node_length_din_b),
			.BD_public_used                    (BD_public_used),
			.mem_management_init_done          (mem_management_init_done),
			.mem_allocate_request              (mem_allocate_request),
			.mem_allocate_address              (mem_allocate_address),
			.mem_free_BD_fifo_empty            (mem_free_BD_fifo_empty),
			.enqueue_Linked_list_ram_wren      (enqueue_Linked_list_ram_wren),
			.enqueue_Linked_list_ram_waddr     (enqueue_Linked_list_ram_waddr),
			.enqueue_Linked_list_ram_wdata     (enqueue_Linked_list_ram_wdata),
			.enqueue_BD_public_used_update_en  (enqueue_BD_public_used_update_en),
			.enqueue_BD_public_used_update_num (enqueue_BD_public_used_update_num),
			.enqueue_executing_flag            (enqueue_executing_flag),
			.enqueue_number_reg                (enqueue_number),
			.queue_head_update_done            (queue_head_update_done),
			.dequeue_executing_flag            (dequeue_executing_flag),
			.dequeue_number                	   (dequeue_number),
			.sr_rx_mul_fifo_full               (sr_rx_mul_fifo_full),
			.sr_rx_mul_fifo_wren               (sr_rx_mul_fifo_wren),
			.sr_rx_mul_fifo_wdata              (sr_rx_mul_fifo_wdata),
			.enqueue_result_fifo_full          (enqueue_result_fifo_full),
			.enqueue_result_fifo_wren          (enqueue_result_fifo_wren),
			.enqueue_result_fifo_wdata         (enqueue_result_fifo_wdata)
		);
`ifdef ASIC
enqueue_result_fifo_fwft inst_enqueue_result_fifo_asic (
	.clk(clk),
	.clr(rst_n),
    .ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(enqueue_result_fifo_wdata),
	.w_we(enqueue_result_fifo_wren),
	.w_full(),
	.w_afull(enqueue_result_fifo_full),
	                          
	.r_data(enqueue_result_fifo_rdata),
	.r_re(enqueue_result_fifo_rden),
	.r_empty(enqueue_result_fifo_empty),
	.r_aempty()
);
`else
enqueue_result_fifo inst_enqueue_result_fifo (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(enqueue_result_fifo_wdata),                  // input wire [0 : 0] din
  .wr_en(enqueue_result_fifo_wren),              // input wire wr_en
  .rd_en(enqueue_result_fifo_rden),              // input wire rd_en
  .dout(enqueue_result_fifo_rdata),                // output wire [0 : 0] dout
  .full(/*full*/),                // output wire full
  .almost_full(enqueue_result_fifo_full),  // output wire almost_full
  .empty(enqueue_result_fifo_empty)              // output wire empty
);
`endif 
`ifdef ASIC
sr_rx_fifo_fwft inst_sr_rx_fifo_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(sr_rx_fifo_wdata),
	.w_we(sr_rx_fifo_wren),
	.w_full(),
	.w_afull(sr_rx_fifo_full),
	
	.r_data(sr_rx_fifo_rdata),
	.r_re(sr_rx_fifo_rden),
	.r_empty(sr_rx_fifo_empty),
	.r_aempty()
);
`else
sr_rx_fifo inst_sr_rx_fifo (
  .clk(clk),                // input wire clk
  .rst(rst),                // input wire rst
  .din(sr_rx_fifo_wdata),                // input wire [39 : 0] din
  .wr_en(sr_rx_fifo_wren),            // input wire wr_en
  .rd_en(sr_rx_fifo_rden),            // input wire rd_en
  .dout(sr_rx_fifo_rdata),              // output wire [39 : 0] dout
  .full(),              // output wire full
  .empty(sr_rx_fifo_empty),            // output wire empty
  .prog_full(sr_rx_fifo_full)  // output wire [6 : 0] data_count
);
`endif
`ifdef ASIC
sr_rx_mul_fifo_fwft inst_sr_rx_mul_fifo_asic(
.clk(clk),
.clr(rst_n),
.ram_2p_cfg_register(ram_2p_cfg_register),                    
.w_data(sr_rx_mul_fifo_wdata),
.w_we(sr_rx_mul_fifo_wren),
.w_full(),
.w_afull(sr_rx_mul_fifo_full),
                          
.r_data(sr_rx_mul_fifo_rdata),
.r_re(sr_rx_mul_fifo_rden),
.r_empty(sr_rx_mul_fifo_empty),
.r_aempty()
);
`else
sr_rx_mul_fifo inst_sr_rx_mul_fifo (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(sr_rx_mul_fifo_wdata),                  // input wire [3 : 0] din
  .wr_en(sr_rx_mul_fifo_wren),              // input wire wr_en
  .rd_en(sr_rx_mul_fifo_rden),              // input wire rd_en
  .dout(sr_rx_mul_fifo_rdata),                // output wire [3 : 0] dout
  .full(/*full*/),                // output wire full
  .almost_full(sr_rx_mul_fifo_full),  // output wire almost_full
  .empty(sr_rx_mul_fifo_empty)              // output wire empty
);
`endif
	queue_infor_management inst_queue_infor_management(
			.clk                             (clk),
			.rst_n                           (rst_n),
			.enqueue_head_infor_wr_en        (enqueue_head_infor_wr_en),
			.enqueue_head_infor_wr_addr      (enqueue_head_infor_wr_addr),
			.enqueue_head_infor_wr_data      (enqueue_head_infor_wr_data),
			.enqueue_head_infor_rd_data      (enqueue_head_infor_rd_data),
			.enqueue_tail_infor_wr_en        (enqueue_tail_infor_wr_en),
			.enqueue_tail_infor_wr_addr      (enqueue_tail_infor_wr_addr),
			.enqueue_tail_infor_wr_data      (enqueue_tail_infor_wr_data),
			.enqueue_tail_infor_rd_data      (enqueue_tail_infor_rd_data),
			.enqueue_length_infor_wr_en      (enqueue_length_infor_wr_en),
			.enqueue_length_infor_wr_addr    (enqueue_length_infor_wr_addr),
			.enqueue_length_infor_wr_data    (enqueue_length_infor_wr_data),
			.enqueue_length_infor_rd_data    (enqueue_length_infor_rd_data),
			// .queue_length_wren_b             (queue_length_wren_b),
			// .queue_length_addr_b             (queue_length_addr_b),
			// .queue_length_din_b              (queue_length_din_b),
			.enqueue_node_length_wr_en       (enqueue_node_length_wr_en),
			.enqueue_node_length_wr_addr     (enqueue_node_length_wr_addr),
			.enqueue_node_length_wr_data     (enqueue_node_length_wr_data),
			.enqueue_node_length_rd_data     (enqueue_node_length_rd_data),
			// .node_length_wren_b              (node_length_wren_b),
			// .node_length_addr_b              (node_length_addr_b),
			// .node_length_din_b               (node_length_din_b),
			.dequeue_head_infor_wr_en        (dequeue_head_infor_wr_en),
			.dequeue_head_infor_wr_addr      (dequeue_head_infor_wr_addr),
			.dequeue_head_infor_wr_data      (dequeue_head_infor_wr_data),
			.dequeue_head_infor_rd_data      (dequeue_head_infor_rd_data),
			.dequeue_tail_infor_wr_en        (dequeue_tail_infor_wr_en),
			.dequeue_tail_infor_wr_addr      (dequeue_tail_infor_wr_addr),
			.dequeue_tail_infor_wr_data      (dequeue_tail_infor_wr_data),
			// .dequeue_tail_infor_rd_data      (dequeue_tail_infor_rd_data),
			.dequeue_length_infor_wr_en      (dequeue_length_infor_wr_en),
			.dequeue_length_infor_wr_addr    (dequeue_length_infor_wr_addr),
			.dequeue_length_infor_wr_data    (dequeue_length_infor_wr_data),
			.dequeue_length_infor_rd_data    (dequeue_length_infor_rd_data),
			// .queue_length_wren_a             (queue_length_wren_a),
			// .queue_length_addr_a             (queue_length_addr_a),
			// .queue_length_din_a              (queue_length_din_a),
			.dequeue_node_length_wr_en       (dequeue_node_length_wr_en),
			.dequeue_node_length_wr_addr     (dequeue_node_length_wr_addr),
			.dequeue_node_length_wr_data     (dequeue_node_length_wr_data),
			.dequeue_node_length_rd_data     (dequeue_node_length_rd_data)
			// .node_length_wren_a              (node_length_wren_a),
			// .node_length_addr_a              (node_length_addr_a),
			// .node_length_din_a               (node_length_din_a)
			// .enqueue_indicate_length_wr_en   (enqueue_indicate_length_wr_en),
			// .enqueue_indicate_length_wr_addr (enqueue_indicate_length_wr_addr),
			// .enqueue_indicate_length_wr_data (enqueue_indicate_length_wr_data),
			// .enqueue_indicate_length_rd_data (enqueue_indicate_length_rd_data),
			// .indicate_length_wren_b          (indicate_length_wren_b),
			// .indicate_length_addr_b          (indicate_length_addr_b),
			// .indicate_length_din_b           (indicate_length_din_b),
			// .dequeue_indicate_length_wr_en   (dequeue_indicate_length_wr_en),
			// .dequeue_indicate_length_wr_addr (dequeue_indicate_length_wr_addr),
			// .dequeue_indicate_length_wr_data (dequeue_indicate_length_wr_data),
			// .dequeue_indicate_length_rd_data (dequeue_indicate_length_rd_data),
			// .indicate_length_wren_a          (indicate_length_wren_a),
			// .indicate_length_addr_a          (indicate_length_addr_a),
			// .indicate_length_din_a           (indicate_length_din_a)
		);

	mem_management inst_mem_management(
			.clk                               (clk),
			.rst_n                             (rst_n),
            .ram_2p_cfg_register               (ram_2p_cfg_register),
			.BD_public_used                    (BD_public_used),
			.mem_management_init_done          (mem_management_init_done),
			.mem_allocate_request              (mem_allocate_request),
			.mem_allocate_address              (mem_allocate_address),
			.mem_free_BD_fifo_empty            (mem_free_BD_fifo_empty),
			.enqueue_Linked_list_ram_wren      (enqueue_Linked_list_ram_wren),
			.enqueue_Linked_list_ram_waddr     (enqueue_Linked_list_ram_waddr),
			.enqueue_Linked_list_ram_wdata     (enqueue_Linked_list_ram_wdata),
			.enqueue_BD_public_used_update_en  (enqueue_BD_public_used_update_en),
			.enqueue_BD_public_used_update_num (enqueue_BD_public_used_update_num),
			.dequeue_BD_public_used_update_en  (dequeue_BD_public_used_update_en),
			.dequeue_BD_public_used_update_num (dequeue_BD_public_used_update_num),
			.dequeue_Linked_list_ram_raddr     (dequeue_Linked_list_ram_raddr),
			.dequeue_Linked_list_ram_rdata     (dequeue_Linked_list_ram_rdata),
			.release_addr_fifo_empty           (release_addr_fifo_empty),
			.release_addr_fifo_rden            (release_addr_fifo_rden),
			.release_addr_fifo_rdata           (release_addr_fifo_rdata),
			.ro_reg_np_freeblocknumber_register(ro_reg_np_freeblocknumber_register)
		);

	bus_master_rx inst_bus_master_rx(
			.clk                             (clk),
			.rst_n                           (rst_n),
            .ram_2p_cfg_register             (ram_2p_cfg_register),
			.enqueue_result_fifo_empty       (enqueue_result_fifo_empty),
			.enqueue_result_fifo_rden        (enqueue_result_fifo_rden),
			.enqueue_result_fifo_rdata       (enqueue_result_fifo_rdata),
			.sr_rx_fifo_empty                (sr_rx_fifo_empty),
			.sr_rx_fifo_rden                 (sr_rx_fifo_rden),
			.sr_rx_fifo_rdata                (sr_rx_fifo_rdata),
			.trans_ready                     (trans_ready),
			.trans_start                     (trans_start),
			.discard_start 			 (discard_start),
			.frame_rd_end 					 (frame_rd_end),
			.bus_data_i                      (bus_data_i),
			.bus_data_val_i                  (bus_data_val_i),
			//.bus_data_end_i                  (bus_data_end_i),
			//.frame_len_bus                   (frame_len_bus),
			.memory_waddr                    (memory_waddr),
			.memory_wren                     (memory_wren),
			.memory_wdata                    (memory_wdata),
			.queue_indicate_ram_init_done    (queue_indicate_ram_init_done   ),
			.enqueue_indicate_length_wr_addr (enqueue_indicate_length_wr_addr),
			.enqueue_indicate_length_wr_data (enqueue_indicate_length_wr_data),
			.enqueue_indicate_length_wr_en   (enqueue_indicate_length_wr_en  ),
			.enqueue_indicate_length_rd_data (enqueue_indicate_length_rd_data),
			.dequeue_indicate_length_wr_addr (dequeue_indicate_length_wr_addr),
			.dequeue_indicate_length_wr_data (dequeue_indicate_length_wr_data),
			.dequeue_indicate_length_wr_en   (dequeue_indicate_length_wr_en  ),
			.port_state_bit_set              (port_state_bit_set),
			.port_state_bit_val 			 (port_state_bit_val)
		);
`ifdef ASIC
ram_2p_d16384_w256_wrapper shared_buffer_ram_asic(
	.clk(clk),
    .ram_2p_cfg_register(ram_2p_cfg_register),
	.wren(memory_wren),
	.waddr(memory_waddr),
	.wdata(memory_wdata),
	.rden(memory_rden),
	.raddr(memory_raddr),
	.rdata(memory_rdata)
);
`else
	SDP_RAM_W256_D16384 shared_buffer_ram (
			.clka (clk         ),  // input wire clka
			.wea  (memory_wren ),  // input wire [0 : 0] wea
			.addra(memory_waddr),  // input wire [13 : 0] addra
			.dina (memory_wdata),  // input wire [255 : 0] dina
			.clkb (clk         ),  // input wire clkb
			.enb  (memory_rden ),  // input wire enb
			.addrb(memory_raddr),  // input wire [13 : 0] addrb
			.doutb(memory_rdata)   // output wire [255 : 0] doutb
		);
`endif
	// port_state_bit_mux inst_port_state_bit_mux(
	// 		.rst_n                (rst_n),
	// 		.clk                  (clk),
	// 		.port_state_bit_set   (port_state_bit_set),
	// 		.port_state_bit_clear (port_state_bit_clear),
	// 		.port_state_bit       (port_state_bit)
	// 	);

	tx_request_gen inst_tx_request_gen(
			.clk                             (clk),
			.rst_n                           (rst_n),
			`ifdef NO_CPU_MODE
			.DWRR_en                         (DWRR_en),
			`else
			.DWRR_en                         (DWRR_en[0]),
			`endif
			.port_state_bit_set   			 (port_state_bit_set),
			.port_state_bit_val   			 (port_state_bit_val),
			.dequeue_indicate_length_wr_en   (dequeue_indicate_length_wr_en),
			.dequeue_indicate_length_wr_addr (dequeue_indicate_length_wr_addr),
			.dequeue_indicate_length_wr_data (dequeue_indicate_length_wr_data),
			.enqueue_indicate_length_wr_en   (enqueue_indicate_length_wr_en),
			.enqueue_indicate_length_wr_addr (enqueue_indicate_length_wr_addr),
			.enqueue_indicate_length_wr_data (enqueue_indicate_length_wr_data),
			.enqueue_indicate_length_rd_data (enqueue_indicate_length_rd_data),
			.tx_fifo_full_mul                (tx_fifo_full_mul),
			.tx_fifo_wren_mul                (tx_fifo_wren_mul),
			.tx_fifo_wdata_mul               (tx_fifo_wdata_mul),
			.tx_fifo_full_7                  (tx_fifo_full_7),
			.tx_fifo_wren_7                  (tx_fifo_wren_7),
			.tx_fifo_wdata_7                 (tx_fifo_wdata_7),
			.tx_fifo_full_6                  (tx_fifo_full_6),
			.tx_fifo_wren_6                  (tx_fifo_wren_6),
			.tx_fifo_wdata_6                 (tx_fifo_wdata_6),
			.tx_fifo_full_5                  (tx_fifo_full_5),
			.tx_fifo_wren_5                  (tx_fifo_wren_5),
			.tx_fifo_wdata_5                 (tx_fifo_wdata_5),
			.tx_fifo_full_4                  (tx_fifo_full_4),
			.tx_fifo_wren_4                  (tx_fifo_wren_4),
			.tx_fifo_wdata_4                 (tx_fifo_wdata_4),
			.tx_fifo_full_3                  (tx_fifo_full_3),
			.tx_fifo_wren_3                  (tx_fifo_wren_3),
			.tx_fifo_wdata_3                 (tx_fifo_wdata_3),
			.tx_fifo_full_2                  (tx_fifo_full_2),
			.tx_fifo_wren_2                  (tx_fifo_wren_2),
			.tx_fifo_wdata_2                 (tx_fifo_wdata_2),
			.tx_fifo_full_1                  (tx_fifo_full_1),
			.tx_fifo_wren_1                  (tx_fifo_wren_1),
			.tx_fifo_wdata_1                 (tx_fifo_wdata_1),
			.tx_fifo_full_0                  (tx_fifo_full_0),
			.tx_fifo_wren_0                  (tx_fifo_wren_0),
			.tx_fifo_wdata_0                 (tx_fifo_wdata_0),
			.uni_tx_rdy0                     (uni_port_val0),
			.uni_tx_rdy1                     (uni_port_val1),
			.uni_tx_rdy2                     (uni_port_val2),
			.uni_tx_rdy3                     (uni_port_val3),
			.mul_tx_rdy0                     (mul_port_val0),
			.mul_tx_rdy1                     (mul_port_val1),
			.mul_tx_rdy2                     (mul_port_val2),
			.mul_tx_rdy3                     (mul_port_val3),
			.sr_rx_mul_fifo_empty            (sr_rx_mul_fifo_empty),
			.sr_rx_mul_fifo_rden             (sr_rx_mul_fifo_rden),
			.sr_rx_mul_fifo_rdata            (sr_rx_mul_fifo_rdata)
		);
`ifdef ASIC
tx_fifo_mul_fwft inst_tx_fifo_mul_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(tx_fifo_wdata_mul),
	.w_we(tx_fifo_wren_mul),
	.w_full(),
	.w_afull(tx_fifo_full_mul),

	.r_data(tx_fifo_rdata_mul),
	.r_re(tx_fifo_rden_mul),
	.r_empty(tx_fifo_empty_mul),
	.r_aempty()	
);
`else
tx_fifo_mul inst_tx_fifo_mul (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(tx_fifo_wdata_mul),                  // input wire [9 : 0] din
  .wr_en(tx_fifo_wren_mul),              // input wire wr_en
  .rd_en(tx_fifo_rden_mul),              // input wire rd_en
  .dout(tx_fifo_rdata_mul),                // output wire [9 : 0] dout
  .full(/*full*/),                // output wire full
  .almost_full(tx_fifo_full_mul),  // output wire almost_full
  .empty(tx_fifo_empty_mul)              // output wire empty
);
`endif

`ifdef ASIC
tx_fifo_uni_fwft inst_tx_fifo_7_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(tx_fifo_wdata_7),
	.w_we(tx_fifo_wren_7),
	.w_full(),
	.w_afull(tx_fifo_full_7),
	
	.r_data(tx_fifo_rdata_7),
	.r_re(tx_fifo_rden_7),
	.r_empty(tx_fifo_empty_7),
	.r_aempty()
);
tx_fifo_uni_fwft inst_tx_fifo_6_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(tx_fifo_wdata_6),
	.w_we(tx_fifo_wren_6),
	.w_full(),
	.w_afull(tx_fifo_full_6),
	
	.r_data(tx_fifo_rdata_6),
	.r_re(tx_fifo_rden_6),
	.r_empty(tx_fifo_empty_6),
	.r_aempty()
);
tx_fifo_uni_fwft inst_tx_fifo_5_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(tx_fifo_wdata_5),
	.w_we(tx_fifo_wren_5),
	.w_full(),
	.w_afull(tx_fifo_full_5),
	
	.r_data(tx_fifo_rdata_5),
	.r_re(tx_fifo_rden_5),
	.r_empty(tx_fifo_empty_5),
	.r_aempty()
);
tx_fifo_uni_fwft inst_tx_fifo_4_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(tx_fifo_wdata_4),
	.w_we(tx_fifo_wren_4),
	.w_full(),
	.w_afull(tx_fifo_full_4),
	
	.r_data(tx_fifo_rdata_4),
	.r_re(tx_fifo_rden_4),
	.r_empty(tx_fifo_empty_4),
	.r_aempty()
);
tx_fifo_uni_fwft inst_tx_fifo_3_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(tx_fifo_wdata_3),
	.w_we(tx_fifo_wren_3),
	.w_full(),
	.w_afull(tx_fifo_full_3),
	
	.r_data(tx_fifo_rdata_3),
	.r_re(tx_fifo_rden_3),
	.r_empty(tx_fifo_empty_3),
	.r_aempty()
);
tx_fifo_uni_fwft inst_tx_fifo_2_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(tx_fifo_wdata_2),
	.w_we(tx_fifo_wren_2),
	.w_full(),
	.w_afull(tx_fifo_full_2),
	
	.r_data(tx_fifo_rdata_2),
	.r_re(tx_fifo_rden_2),
	.r_empty(tx_fifo_empty_2),
	.r_aempty()
);
tx_fifo_uni_fwft inst_tx_fifo_1_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(tx_fifo_wdata_1),
	.w_we(tx_fifo_wren_1),
	.w_full(),
	.w_afull(tx_fifo_full_1),
	
	.r_data(tx_fifo_rdata_1),
	.r_re(tx_fifo_rden_1),
	.r_empty(tx_fifo_empty_1),
	.r_aempty()
);
tx_fifo_uni_fwft inst_tx_fifo_0_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(tx_fifo_wdata_0),
	.w_we(tx_fifo_wren_0),
	.w_full(),
	.w_afull(tx_fifo_full_0),
	
	.r_data(tx_fifo_rdata_0),
	.r_re(tx_fifo_rden_0),
	.r_empty(tx_fifo_empty_0),
	.r_aempty()
);
`else
tx_fifo_uni inst_tx_fifo_7 (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(tx_fifo_wdata_7),                  // input wire [5 : 0] din
  .wr_en(tx_fifo_wren_7),              // input wire wr_en
  .rd_en(tx_fifo_rden_7),              // input wire rd_en
  .dout(tx_fifo_rdata_7),                // output wire [5 : 0] dout
  .full(/*full*/),                // output wire full
  .almost_full(tx_fifo_full_7),  // output wire almost_full
  .empty(tx_fifo_empty_7)              // output wire empty
);

tx_fifo_uni inst_tx_fifo_6 (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(tx_fifo_wdata_6),                  // input wire [5 : 0] din
  .wr_en(tx_fifo_wren_6),              // input wire wr_en
  .rd_en(tx_fifo_rden_6),              // input wire rd_en
  .dout(tx_fifo_rdata_6),                // output wire [5 : 0] dout
  .full(/*full*/),                // output wire full
  .almost_full(tx_fifo_full_6),  // output wire almost_full
  .empty(tx_fifo_empty_6)              // output wire empty
);

tx_fifo_uni inst_tx_fifo_5 (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(tx_fifo_wdata_5),                  // input wire [5 : 0] din
  .wr_en(tx_fifo_wren_5),              // input wire wr_en
  .rd_en(tx_fifo_rden_5),              // input wire rd_en
  .dout(tx_fifo_rdata_5),                // output wire [5 : 0] dout
  .full(/*full*/),                // output wire full
  .almost_full(tx_fifo_full_5),  // output wire almost_full
  .empty(tx_fifo_empty_5)              // output wire empty
);

tx_fifo_uni inst_tx_fifo_4 (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(tx_fifo_wdata_4),                  // input wire [5 : 0] din
  .wr_en(tx_fifo_wren_4),              // input wire wr_en
  .rd_en(tx_fifo_rden_4),              // input wire rd_en
  .dout(tx_fifo_rdata_4),                // output wire [5 : 0] dout
  .full(/*full*/),                // output wire full
  .almost_full(tx_fifo_full_4),  // output wire almost_full
  .empty(tx_fifo_empty_4)              // output wire empty
);

tx_fifo_uni inst_tx_fifo_3 (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(tx_fifo_wdata_3),                  // input wire [5 : 0] din
  .wr_en(tx_fifo_wren_3),              // input wire wr_en
  .rd_en(tx_fifo_rden_3),              // input wire rd_en
  .dout(tx_fifo_rdata_3),                // output wire [5 : 0] dout
  .full(/*full*/),                // output wire full
  .almost_full(tx_fifo_full_3),  // output wire almost_full
  .empty(tx_fifo_empty_3)              // output wire empty
);

tx_fifo_uni inst_tx_fifo_2 (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(tx_fifo_wdata_2),                  // input wire [5 : 0] din
  .wr_en(tx_fifo_wren_2),              // input wire wr_en
  .rd_en(tx_fifo_rden_2),              // input wire rd_en
  .dout(tx_fifo_rdata_2),                // output wire [5 : 0] dout
  .full(/*full*/),                // output wire full
  .almost_full(tx_fifo_full_2),  // output wire almost_full
  .empty(tx_fifo_empty_2)              // output wire empty
);

tx_fifo_uni inst_tx_fifo_1 (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(tx_fifo_wdata_1),                  // input wire [5 : 0] din
  .wr_en(tx_fifo_wren_1),              // input wire wr_en
  .rd_en(tx_fifo_rden_1),              // input wire rd_en
  .dout(tx_fifo_rdata_1),                // output wire [5 : 0] dout
  .full(/*full*/),                // output wire full
  .almost_full(tx_fifo_full_1),  // output wire almost_full
  .empty(tx_fifo_empty_1)              // output wire empty
);

tx_fifo_uni inst_tx_fifo_0 (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(tx_fifo_wdata_0),                  // input wire [5 : 0] din
  .wr_en(tx_fifo_wren_0),              // input wire wr_en
  .rd_en(tx_fifo_rden_0),              // input wire rd_en
  .dout(tx_fifo_rdata_0),                // output wire [5 : 0] dout
  .full(/*full*/),                // output wire full
  .almost_full(tx_fifo_full_0),  // output wire almost_full
  .empty(tx_fifo_empty_0)              // output wire empty
);
`endif
	schedule_dequeue inst_schedule_dequeue(
			.clk                               (clk),
			.rst_n                             (rst_n),
			.query_CPU_node_min_threshold      (query_CPU_node_min_threshold),
			.CPU_node_min_threshold_data       (CPU_node_min_threshold_data),
			.ro_reg_np_dequeue_num			   (ro_reg_np_dequeue_num),
            .ro_reg_np_max_tx_length           (ro_reg_np_max_tx_length),
            .tx_frame_cnt_node_0               (tx_frame_cnt_node_0),
            .tx_frame_cnt_node_1               (tx_frame_cnt_node_1),
            .tx_frame_cnt_node_2               (tx_frame_cnt_node_2),
            .tx_frame_cnt_node_3               (tx_frame_cnt_node_3),
            .tx_frame_cnt_node_4               (tx_frame_cnt_node_4),
			.queue_mem_init_done               (queue_mem_init_done),
			.enqueue_executing_flag            (enqueue_executing_flag),
			.enqueue_number                    (enqueue_number),
			.queue_head_update_done            (queue_head_update_done),
			.dequeue_executing_flag            (dequeue_executing_flag),
			.dequeue_number_reg                (dequeue_number),
			.enqueue_Linked_list_ram_wren      (enqueue_Linked_list_ram_wren),
			.enqueue_Linked_list_ram_waddr     (enqueue_Linked_list_ram_waddr),
			.enqueue_Linked_list_ram_wdata     (enqueue_Linked_list_ram_wdata),
			.dequeue_head_infor_wr_en          (dequeue_head_infor_wr_en),
			.dequeue_head_infor_wr_addr        (dequeue_head_infor_wr_addr),
			.dequeue_head_infor_wr_data        (dequeue_head_infor_wr_data),
			.dequeue_head_infor_rd_data        (dequeue_head_infor_rd_data),
			.dequeue_tail_infor_wr_en          (dequeue_tail_infor_wr_en),
			.dequeue_tail_infor_wr_addr        (dequeue_tail_infor_wr_addr),
			.dequeue_tail_infor_wr_data        (dequeue_tail_infor_wr_data),
			// .dequeue_tail_infor_rd_data        (dequeue_tail_infor_rd_data),
			.dequeue_length_infor_wr_en        (dequeue_length_infor_wr_en),
			.dequeue_length_infor_wr_addr      (dequeue_length_infor_wr_addr),
			.dequeue_length_infor_wr_data      (dequeue_length_infor_wr_data),
			.dequeue_length_infor_rd_data      (dequeue_length_infor_rd_data),
			.enqueue_length_infor_wr_en        (enqueue_length_infor_wr_en),
			.enqueue_length_infor_wr_addr      (enqueue_length_infor_wr_addr),
			.enqueue_length_infor_wr_data      (enqueue_length_infor_wr_data),
			// .queue_length_wren_a               (queue_length_wren_a),
			// .queue_length_addr_a               (queue_length_addr_a),
			// .queue_length_din_a                (queue_length_din_a),
			.dequeue_node_length_wr_en         (dequeue_node_length_wr_en),
			.dequeue_node_length_wr_addr       (dequeue_node_length_wr_addr),
			.dequeue_node_length_wr_data       (dequeue_node_length_wr_data),
			.dequeue_node_length_rd_data       (dequeue_node_length_rd_data),
			.enqueue_node_length_wr_en         (enqueue_node_length_wr_en),
			.enqueue_node_length_wr_addr       (enqueue_node_length_wr_addr),
			.enqueue_node_length_wr_data       (enqueue_node_length_wr_data),			
			// .node_length_wren_a                (node_length_wren_a),
			// .node_length_addr_a                (node_length_addr_a),
			// .node_length_din_a                 (node_length_din_a),
			.dequeue_Linked_list_ram_raddr     (dequeue_Linked_list_ram_raddr),
			.dequeue_Linked_list_ram_rdata     (dequeue_Linked_list_ram_rdata),
			.dequeue_BD_public_used_update_en  (dequeue_BD_public_used_update_en),
			.dequeue_BD_public_used_update_num (dequeue_BD_public_used_update_num),
			.tx_fifo_empty_mul                 (tx_fifo_empty_mul),
			.tx_fifo_rden_mul                  (tx_fifo_rden_mul),
			.tx_fifo_rdata_mul                 (tx_fifo_rdata_mul),
			.tx_fifo_empty_7                   (tx_fifo_empty_7),
			.tx_fifo_rden_7                    (tx_fifo_rden_7),
			.tx_fifo_rdata_7                   (tx_fifo_rdata_7),
			.tx_fifo_empty_6                   (tx_fifo_empty_6),
			.tx_fifo_rden_6                    (tx_fifo_rden_6),
			.tx_fifo_rdata_6                   (tx_fifo_rdata_6),
			.tx_fifo_empty_5                   (tx_fifo_empty_5),
			.tx_fifo_rden_5                    (tx_fifo_rden_5),
			.tx_fifo_rdata_5                   (tx_fifo_rdata_5),
			.tx_fifo_empty_4                   (tx_fifo_empty_4),
			.tx_fifo_rden_4                    (tx_fifo_rden_4),
			.tx_fifo_rdata_4                   (tx_fifo_rdata_4),
			.tx_fifo_empty_3                   (tx_fifo_empty_3),
			.tx_fifo_rden_3                    (tx_fifo_rden_3),
			.tx_fifo_rdata_3                   (tx_fifo_rdata_3),
			.tx_fifo_empty_2                   (tx_fifo_empty_2),
			.tx_fifo_rden_2                    (tx_fifo_rden_2),
			.tx_fifo_rdata_2                   (tx_fifo_rdata_2),
			.tx_fifo_empty_1                   (tx_fifo_empty_1),
			.tx_fifo_rden_1                    (tx_fifo_rden_1),
			.tx_fifo_rdata_1                   (tx_fifo_rdata_1),
			.tx_fifo_empty_0                   (tx_fifo_empty_0),
			.tx_fifo_rden_0                    (tx_fifo_rden_0),
			.tx_fifo_rdata_0                   (tx_fifo_rdata_0),
			.sr_tx_fifo_full_mul               (sr_tx_fifo_full_mul),
			.sr_tx_fifo_wren_mul               (sr_tx_fifo_wren_mul),
			.sr_tx_fifo_wdata_mul              (sr_tx_fifo_wdata_mul),
			// .sr_tx_fifo_cnt_mul                (sr_tx_fifo_cnt_mul),
			.sr_tx_fifo_full_7                 (sr_tx_fifo_full_7),
			.sr_tx_fifo_wren_7                 (sr_tx_fifo_wren_7),
			.sr_tx_fifo_wdata_7                (sr_tx_fifo_wdata_7),
			// .sr_tx_fifo_cnt_7                  (sr_tx_fifo_cnt_7),
			.sr_tx_fifo_full_6                 (sr_tx_fifo_full_6),
			.sr_tx_fifo_wren_6                 (sr_tx_fifo_wren_6),
			.sr_tx_fifo_wdata_6                (sr_tx_fifo_wdata_6),
			// .sr_tx_fifo_cnt_6                  (sr_tx_fifo_cnt_6),
			.sr_tx_fifo_full_5                 (sr_tx_fifo_full_5),
			.sr_tx_fifo_wren_5                 (sr_tx_fifo_wren_5),
			.sr_tx_fifo_wdata_5                (sr_tx_fifo_wdata_5),
			// .sr_tx_fifo_cnt_5                  (sr_tx_fifo_cnt_5),
			.sr_tx_fifo_full_4                 (sr_tx_fifo_full_4),
			.sr_tx_fifo_wren_4                 (sr_tx_fifo_wren_4),
			.sr_tx_fifo_wdata_4                (sr_tx_fifo_wdata_4),
			// .sr_tx_fifo_cnt_4                  (sr_tx_fifo_cnt_4),
			.sr_tx_fifo_full_3                 (sr_tx_fifo_full_3),
			.sr_tx_fifo_wren_3                 (sr_tx_fifo_wren_3),
			.sr_tx_fifo_wdata_3                (sr_tx_fifo_wdata_3),
			// .sr_tx_fifo_cnt_3                  (sr_tx_fifo_cnt_3),
			.sr_tx_fifo_full_2                 (sr_tx_fifo_full_2),
			.sr_tx_fifo_wren_2                 (sr_tx_fifo_wren_2),
			.sr_tx_fifo_wdata_2                (sr_tx_fifo_wdata_2),
			// .sr_tx_fifo_cnt_2                  (sr_tx_fifo_cnt_2),
			.sr_tx_fifo_full_1                 (sr_tx_fifo_full_1),
			.sr_tx_fifo_wren_1                 (sr_tx_fifo_wren_1),
			.sr_tx_fifo_wdata_1                (sr_tx_fifo_wdata_1),
			// .sr_tx_fifo_cnt_1                  (sr_tx_fifo_cnt_1),
			.sr_tx_fifo_full_0                 (sr_tx_fifo_full_0),
			.sr_tx_fifo_wren_0                 (sr_tx_fifo_wren_0),
			.sr_tx_fifo_wdata_0                (sr_tx_fifo_wdata_0)
			// .sr_tx_fifo_cnt_0                  (sr_tx_fifo_cnt_0)
		);
`ifdef ASIC
sr_tx_fifo_fwft inst_sr_tx_fifo_mul_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(sr_tx_fifo_wdata_mul),
	.w_we(sr_tx_fifo_wren_mul),
	.w_full(),
	.w_afull(sr_tx_fifo_full_mul),
	
	.r_data(sr_tx_fifo_rdata_mul),
	.r_re(sr_tx_fifo_rden_mul),
	.r_empty(sr_tx_fifo_empty_mul),
	.r_aempty()
);
sr_tx_fifo_fwft inst_sr_tx_fifo_7_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(sr_tx_fifo_wdata_7),
	.w_we(sr_tx_fifo_wren_7),
	.w_full(),
	.w_afull(sr_tx_fifo_full_7),
	
	.r_data(sr_tx_fifo_rdata_7),
	.r_re(sr_tx_fifo_rden_7),
	.r_empty(sr_tx_fifo_empty_7),
	.r_aempty()
);
sr_tx_fifo_fwft inst_sr_tx_fifo_6_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(sr_tx_fifo_wdata_6),
	.w_we(sr_tx_fifo_wren_6),
	.w_full(),
	.w_afull(sr_tx_fifo_full_6),
	
	.r_data(sr_tx_fifo_rdata_6),
	.r_re(sr_tx_fifo_rden_6),
	.r_empty(sr_tx_fifo_empty_6),
	.r_aempty()
);
sr_tx_fifo_fwft inst_sr_tx_fifo_5_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(sr_tx_fifo_wdata_5),
	.w_we(sr_tx_fifo_wren_5),
	.w_full(),
	.w_afull(sr_tx_fifo_full_5),
	
	.r_data(sr_tx_fifo_rdata_5),
	.r_re(sr_tx_fifo_rden_5),
	.r_empty(sr_tx_fifo_empty_5),
	.r_aempty()
);
sr_tx_fifo_fwft inst_sr_tx_fifo_4_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(sr_tx_fifo_wdata_4),
	.w_we(sr_tx_fifo_wren_4),
	.w_full(),
	.w_afull(sr_tx_fifo_full_4),
	
	.r_data(sr_tx_fifo_rdata_4),
	.r_re(sr_tx_fifo_rden_4),
	.r_empty(sr_tx_fifo_empty_4),
	.r_aempty()
);
sr_tx_fifo_fwft inst_sr_tx_fifo_3_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(sr_tx_fifo_wdata_3),
	.w_we(sr_tx_fifo_wren_3),
	.w_full(),
	.w_afull(sr_tx_fifo_full_3),
	
	.r_data(sr_tx_fifo_rdata_3),
	.r_re(sr_tx_fifo_rden_3),
	.r_empty(sr_tx_fifo_empty_3),
	.r_aempty()
);
sr_tx_fifo_fwft inst_sr_tx_fifo_2_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(sr_tx_fifo_wdata_2),
	.w_we(sr_tx_fifo_wren_2),
	.w_full(),
	.w_afull(sr_tx_fifo_full_2),
	
	.r_data(sr_tx_fifo_rdata_2),
	.r_re(sr_tx_fifo_rden_2),
	.r_empty(sr_tx_fifo_empty_2),
	.r_aempty()
);
sr_tx_fifo_fwft inst_sr_tx_fifo_1_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(sr_tx_fifo_wdata_1),
	.w_we(sr_tx_fifo_wren_1),
	.w_full(),
	.w_afull(sr_tx_fifo_full_1),
	
	.r_data(sr_tx_fifo_rdata_1),
	.r_re(sr_tx_fifo_rden_1),
	.r_empty(sr_tx_fifo_empty_1),
	.r_aempty()
);
sr_tx_fifo_fwft inst_sr_tx_fifo_0_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(sr_tx_fifo_wdata_0),
	.w_we(sr_tx_fifo_wren_0),
	.w_full(),
	.w_afull(sr_tx_fifo_full_0),
	
	.r_data(sr_tx_fifo_rdata_0),
	.r_re(sr_tx_fifo_rden_0),
	.r_empty(sr_tx_fifo_empty_0),
	.r_aempty()
);
`else
sr_tx_fifo inst_sr_tx_fifo_mul (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(sr_tx_fifo_wdata_mul),                  // input wire [47 : 0] din
  .wr_en(sr_tx_fifo_wren_mul),              // input wire wr_en
  .rd_en(sr_tx_fifo_rden_mul),              // input wire rd_en
  .dout(sr_tx_fifo_rdata_mul),                // output wire [47 : 0] dout
  .full(/*full*/),                // output wire full
  // .almost_full(/*sr_tx_fifo_full_mul*/),  // output wire almost_full
  .empty(sr_tx_fifo_empty_mul),              // output wire empty
  // .data_count(sr_tx_fifo_cnt_mul)    // output wire [7 : 0] data_count
  .prog_full(sr_tx_fifo_full_mul)
);

sr_tx_fifo inst_sr_tx_fifo_7 (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(sr_tx_fifo_wdata_7),                  // input wire [47 : 0] din
  .wr_en(sr_tx_fifo_wren_7),              // input wire wr_en
  .rd_en(sr_tx_fifo_rden_7),              // input wire rd_en
  .dout(sr_tx_fifo_rdata_7),                // output wire [47 : 0] dout
  .full(/*full*/),                // output wire full
  // .almost_full(/*sr_tx_fifo_full_7*/),  // output wire almost_full
  .empty(sr_tx_fifo_empty_7),              // output wire empty
  // .data_count(sr_tx_fifo_cnt_7)    // output wire [7 : 0] data_count
  .prog_full(sr_tx_fifo_full_7)
);

sr_tx_fifo inst_sr_tx_fifo_6 (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(sr_tx_fifo_wdata_6),                  // input wire [47 : 0] din
  .wr_en(sr_tx_fifo_wren_6),              // input wire wr_en
  .rd_en(sr_tx_fifo_rden_6),              // input wire rd_en
  .dout(sr_tx_fifo_rdata_6),                // output wire [47 : 0] dout
  .full(/*full*/),                // output wire full
  // .almost_full(/*sr_tx_fifo_full_6*/),  // output wire almost_full
  .empty(sr_tx_fifo_empty_6),              // output wire empty
  // .data_count(sr_tx_fifo_cnt_6)    // output wire [7 : 0] data_count
  .prog_full(sr_tx_fifo_full_6)
);

sr_tx_fifo inst_sr_tx_fifo_5 (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(sr_tx_fifo_wdata_5),                  // input wire [47 : 0] din
  .wr_en(sr_tx_fifo_wren_5),              // input wire wr_en
  .rd_en(sr_tx_fifo_rden_5),              // input wire rd_en
  .dout(sr_tx_fifo_rdata_5),                // output wire [47 : 0] dout
  .full(/*full*/),                // output wire full
  // .almost_full(/*sr_tx_fifo_full_5*/),  // output wire almost_full
  .empty(sr_tx_fifo_empty_5),              // output wire empty
  // .data_count(sr_tx_fifo_cnt_5)    // output wire [7 : 0] data_count
  .prog_full(sr_tx_fifo_full_5)
);

sr_tx_fifo inst_sr_tx_fifo_4 (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(sr_tx_fifo_wdata_4),                  // input wire [47 : 0] din
  .wr_en(sr_tx_fifo_wren_4),              // input wire wr_en
  .rd_en(sr_tx_fifo_rden_4),              // input wire rd_en
  .dout(sr_tx_fifo_rdata_4),                // output wire [47 : 0] dout
  .full(/*full*/),                // output wire full
  // .almost_full(/*sr_tx_fifo_full_4*/),  // output wire almost_full
  .empty(sr_tx_fifo_empty_4),              // output wire empty
  // .data_count(sr_tx_fifo_cnt_4)    // output wire [7 : 0] data_count
  .prog_full(sr_tx_fifo_full_4)
);

sr_tx_fifo inst_sr_tx_fifo_3 (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(sr_tx_fifo_wdata_3),                  // input wire [47 : 0] din
  .wr_en(sr_tx_fifo_wren_3),              // input wire wr_en
  .rd_en(sr_tx_fifo_rden_3),              // input wire rd_en
  .dout(sr_tx_fifo_rdata_3),                // output wire [47 : 0] dout
  .full(/*full*/),                // output wire full
  // .almost_full(/*sr_tx_fifo_full_3*/),  // output wire almost_full
  .empty(sr_tx_fifo_empty_3),              // output wire empty
  // .data_count(sr_tx_fifo_cnt_3)    // output wire [7 : 0] data_count
  .prog_full(sr_tx_fifo_full_3)
);

sr_tx_fifo inst_sr_tx_fifo_2 (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(sr_tx_fifo_wdata_2),                  // input wire [47 : 0] din
  .wr_en(sr_tx_fifo_wren_2),              // input wire wr_en
  .rd_en(sr_tx_fifo_rden_2),              // input wire rd_en
  .dout(sr_tx_fifo_rdata_2),                // output wire [47 : 0] dout
  .full(/*full*/),                // output wire full
  // .almost_full(/*sr_tx_fifo_full_2*/),  // output wire almost_full
  .empty(sr_tx_fifo_empty_2),              // output wire empty
  // .data_count(sr_tx_fifo_cnt_2)    // output wire [7 : 0] data_count
  .prog_full(sr_tx_fifo_full_2)
);

sr_tx_fifo inst_sr_tx_fifo_1 (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(sr_tx_fifo_wdata_1),                  // input wire [47 : 0] din
  .wr_en(sr_tx_fifo_wren_1),              // input wire wr_en
  .rd_en(sr_tx_fifo_rden_1),              // input wire rd_en
  .dout(sr_tx_fifo_rdata_1),                // output wire [47 : 0] dout
  .full(full),                // output wire full
  // .almost_full(/*sr_tx_fifo_full_1*/),  // output wire almost_full
  .empty(sr_tx_fifo_empty_1),              // output wire empty
  // .data_count(sr_tx_fifo_cnt_1)    // output wire [7 : 0] data_count
  .prog_full(sr_tx_fifo_full_1)
);

sr_tx_fifo inst_sr_tx_fifo_0 (
  .clk(clk),                  // input wire clk
  .rst(rst),                  // input wire rst
  .din(sr_tx_fifo_wdata_0),                  // input wire [47 : 0] din
  .wr_en(sr_tx_fifo_wren_0),              // input wire wr_en
  .rd_en(sr_tx_fifo_rden_0),              // input wire rd_en
  .dout(sr_tx_fifo_rdata_0),                // output wire [47 : 0] dout
  .full(/*full*/),                // output wire full
  // .almost_full(/*sr_tx_fifo_full_0*/),  // output wire almost_full
  .empty(sr_tx_fifo_empty_0),              // output wire empty
  // .data_count(sr_tx_fifo_cnt_0)    // output wire [7 : 0] data_count
  .prog_full(sr_tx_fifo_full_0)
);
`endif
	bus_master_tx inst_bus_master_tx(
			.clk                     (clk),
			.rst_n                   (rst_n),
			`ifdef NO_CPU_MODE
			.DWRR_en                 (DWRR_en),
			.weight_back_num 		 (16'd200),
			`else
			.DWRR_en                 (DWRR_en[0]),
			.weight_back_num 		 (DWRR_en[16:1]),
			`endif
			.WEIGHT7                 (WEIGHT7),
			.WEIGHT6                 (WEIGHT6),
			.WEIGHT5                 (WEIGHT5),
			.WEIGHT4                 (WEIGHT4),
			.WEIGHT3                 (WEIGHT3),
			.WEIGHT2                 (WEIGHT2),
			.WEIGHT1                 (WEIGHT1),
			.WEIGHT0                 (WEIGHT0),
			.sr_tx_fifo_empty_mul    (sr_tx_fifo_empty_mul),
			.sr_tx_fifo_rden_mul     (sr_tx_fifo_rden_mul),
			.sr_tx_fifo_rdata_mul    (sr_tx_fifo_rdata_mul),
			.sr_tx_fifo_empty_7      (sr_tx_fifo_empty_7),
			.sr_tx_fifo_rden_7       (sr_tx_fifo_rden_7),
			.sr_tx_fifo_rdata_7      (sr_tx_fifo_rdata_7),
			.sr_tx_fifo_empty_6      (sr_tx_fifo_empty_6),
			.sr_tx_fifo_rden_6       (sr_tx_fifo_rden_6),
			.sr_tx_fifo_rdata_6      (sr_tx_fifo_rdata_6),
			.sr_tx_fifo_empty_5      (sr_tx_fifo_empty_5),
			.sr_tx_fifo_rden_5       (sr_tx_fifo_rden_5),
			.sr_tx_fifo_rdata_5      (sr_tx_fifo_rdata_5),
			.sr_tx_fifo_empty_4      (sr_tx_fifo_empty_4),
			.sr_tx_fifo_rden_4       (sr_tx_fifo_rden_4),
			.sr_tx_fifo_rdata_4      (sr_tx_fifo_rdata_4),
			.sr_tx_fifo_empty_3      (sr_tx_fifo_empty_3),
			.sr_tx_fifo_rden_3       (sr_tx_fifo_rden_3),
			.sr_tx_fifo_rdata_3      (sr_tx_fifo_rdata_3),
			.sr_tx_fifo_empty_2      (sr_tx_fifo_empty_2),
			.sr_tx_fifo_rden_2       (sr_tx_fifo_rden_2),
			.sr_tx_fifo_rdata_2      (sr_tx_fifo_rdata_2),
			.sr_tx_fifo_empty_1      (sr_tx_fifo_empty_1),
			.sr_tx_fifo_rden_1       (sr_tx_fifo_rden_1),
			.sr_tx_fifo_rdata_1      (sr_tx_fifo_rdata_1),
			.sr_tx_fifo_empty_0      (sr_tx_fifo_empty_0),
			.sr_tx_fifo_rden_0       (sr_tx_fifo_rden_0),
			.sr_tx_fifo_rdata_0      (sr_tx_fifo_rdata_0),
			.memory_raddr            (memory_raddr),
			.memory_rden             (memory_rden),
			.memory_rdata            (memory_rdata),
			.uni_tx_rdy0             (uni_tx_rdy0),
			.uni_tx_rdy1             (uni_tx_rdy1),
			.uni_tx_rdy2             (uni_tx_rdy2),
			.uni_tx_rdy3             (uni_tx_rdy3),
			.mul_tx_rdy0             (mul_tx_rdy0),
			.mul_tx_rdy1             (mul_tx_rdy1),
			.mul_tx_rdy2             (mul_tx_rdy2),
			.mul_tx_rdy3             (mul_tx_rdy3),
			.emac_data_in            (emac_data_in),
			.emac_data_wren          (emac_data_wren),
			.rx_address_dpram        (rx_address_dpram),
			.mac_dest_port_out    	 (mac_dest_port_in),
			.mul_indicate_out        (mul_indicate),
			.release_addr_fifo_full  (release_addr_fifo_full),
			.release_addr_fifo_wren  (release_addr_fifo_wren),
			.release_addr_fifo_wdata (release_addr_fifo_wdata)
			// .release_addr_fifo_cnt   (release_addr_fifo_cnt)
		);
`ifdef ASIC
release_addr_fifo_fwft inst_release_addr_fifo_asic(
	.clk(clk),
	.clr(rst_n),
	.ram_2p_cfg_register(ram_2p_cfg_register),                          
	.w_data(release_addr_fifo_wdata),
	.w_we(release_addr_fifo_wren),
	.w_full(release_addr_fifo_full),
	.w_afull(),
	                          
	.r_data(release_addr_fifo_rdata),
	.r_re(release_addr_fifo_rden),
	.r_empty(release_addr_fifo_empty),
	.r_aempty()
);
`else
release_addr_fifo inst_release_addr_fifo (
  .clk(clk),                // input wire clk
  .rst(rst),                // input wire rst
  .din(release_addr_fifo_wdata),                // input wire [17 : 0] din
  .wr_en(release_addr_fifo_wren),            // input wire wr_en
  .rd_en(release_addr_fifo_rden),            // input wire rd_en
  .dout(release_addr_fifo_rdata),              // output wire [17 : 0] dout
  .full(/*release_addr_fifo_full*/),              // output wire full
  .empty(release_addr_fifo_empty),            // output wire empty
  // .data_count(release_addr_fifo_cnt)  // output wire [6 : 0] data_count
  .prog_full(release_addr_fifo_full)
);
`endif

`ifndef NO_CPU_MODE
schedule_cpu_interface 
U_schedule_cpu_interface(
	.clk				(clk 		),	
	.rst_n				(rst_n 		),
	//******************************************************************
	//cpu_interface
	//******************************************************************
	//\u961f\u5217&\u7ed3\u70b9\u95e8\u9650
  //cpu interface 
 	.np_data_out		(np_data_out),
 	.np_data_in			(np_data_in	),
 	.np_addr_in 		(np_addr_in ),
 	.np_addr_ctrl 		(np_addr_ctrl ),  
	.sch_rd_vld(sch_rd_vld),
	//******************************************************************
	//queue_shedule interface
	//******************************************************************
	//queue_node threshold
	//	enqueue 
	.query_CPU_node_minmax_threshold 	(query_CPU_node_minmax_threshold),  //\u8282\u70b9\u6700\u5c0f\u6700\u5927\u95e8\u9650
	.CPU_node_minmax_threshold_data  	(CPU_node_minmax_threshold_data ),
	.query_CPU_queue_max_threshold   	(query_CPU_queue_max_threshold  ),  //\u961f\u5217\u6700\u5927\u95e8\u9650
	.CPU_queue_max_threshold_data    	(CPU_queue_max_threshold_data   ),
	.CPU_BD_public_length            	(CPU_BD_public_length           ),  //BD\u5171\u4eab\u533a\u5927\u5c0f
	//	dequeue
	.query_CPU_node_min_threshold		(query_CPU_node_min_threshold 	),
	.CPU_node_min_threshold_data 		(CPU_node_min_threshold_data  	),	


	//rx_tx_frame count
	.rx_frame_cnt_node_0             	(rx_frame_cnt_node_0 			),
	.rx_frame_cnt_node_1             	(rx_frame_cnt_node_1 			),
	.rx_frame_cnt_node_2             	(rx_frame_cnt_node_2 			),
	.rx_frame_cnt_node_3             	(rx_frame_cnt_node_3 			),
	.rx_frame_cnt_node_4             	(rx_frame_cnt_node_4 			),
	.tx_frame_cnt_node_0             	(tx_frame_cnt_node_0 			),
	.tx_frame_cnt_node_1             	(tx_frame_cnt_node_1 			),
	.tx_frame_cnt_node_2             	(tx_frame_cnt_node_2 			),
	.tx_frame_cnt_node_3             	(tx_frame_cnt_node_3 			),
	.tx_frame_cnt_node_4             	(tx_frame_cnt_node_4 			),

  //register 
  	.ro_reg_np_freeblocknumber_register(ro_reg_np_freeblocknumber_register),
  	.ro_reg_np_mac_enqueue_cnt         (ro_reg_np_mac_enqueue_cnt         ),  
  	.ro_reg_np_mac_enqueue_fail_cnt    (ro_reg_np_mac_enqueue_fail_cnt    ), 
  	.ro_reg_np_enqueue_num             (ro_reg_np_enqueue_num             ),       
  	.ro_reg_np_dequeue_num             (ro_reg_np_dequeue_num             ),         
  	.ro_reg_np_max_rx_length           (ro_reg_np_max_rx_length           ),         
  	.ro_reg_np_max_tx_length           (ro_reg_np_max_tx_length           ),


  	.DWRR_en   						   (DWRR_en 						),
  	.WEIGHT7   						   (WEIGHT7 						),
  	.WEIGHT6   						   (WEIGHT6 						),
  	.WEIGHT5   						   (WEIGHT5 						),
  	.WEIGHT4   						   (WEIGHT4 						),
  	.WEIGHT3   						   (WEIGHT3 						),
  	.WEIGHT2   						   (WEIGHT2 						),
  	.WEIGHT1   						   (WEIGHT1 						),
  	.WEIGHT0   						   (WEIGHT0 						)        
	);
`endif

//*********************
//MAIN CORE
//*********************
assign init_done = queue_mem_init_done & mem_management_init_done & queue_indicate_ram_init_done;
assign uni_port_val0 = uni_tx_rdy0 | (mac_dest_port_in[0] & (~mul_indicate));
assign uni_port_val1 = uni_tx_rdy1 | (mac_dest_port_in[1] & (~mul_indicate));
assign uni_port_val2 = uni_tx_rdy2 | (mac_dest_port_in[2] & (~mul_indicate));
assign uni_port_val3 = uni_tx_rdy3 | (mac_dest_port_in[3] & (~mul_indicate));
assign mul_port_val0 = mul_tx_rdy0 | (mac_dest_port_in[0] & mul_indicate);
assign mul_port_val1 = mul_tx_rdy1 | (mac_dest_port_in[1] & mul_indicate);
assign mul_port_val2 = mul_tx_rdy2 | (mac_dest_port_in[2] & mul_indicate);
assign mul_port_val3 = mul_tx_rdy3 | (mac_dest_port_in[3] & mul_indicate);
assign rst = (~rst_n);

endmodule

